Video monitoring system using daisy chain

ABSTRACT

A video monitoring system using daisy chain is disclosed. The video monitoring system can display a multiplexed image consisting of four or more pictures by bypassing video signals captured by a plurality of video cameras through several stages.

FIELD OF THE INVENTION

The present invention relates to a video monitoring system and, moreparticularly, to a video monitoring system using daisy chain.

DESCRIPTION OF THE RELATED ART

A conventional video monitoring system is installed in a house,department store, bank, factory, exhibition hall, etc. to monitorvisitors and to prevent a burglary. The conventional video monitoringsystem includes a plurality of video cameras for capturing video signalscorresponding to objects in monitored areas, a signal processor forprocessing video signals captured by the video cameras, and a videodisplay device for displaying a multiplexed image consisting of aplurality of pictures corresponding to the processed video signals onone display screen.

The conventional video monitoring system scales down video datacorresponding to video signals captured by four video cameras accordingto a predetermined scale-down ratio and displays a multiplexed imageconsisting of four pictures corresponding to the scaled-down video data.Here, the multiplexed image consisting of four pictures is referred toas a quad image. A full screen image, or a multiplexed image consistingof four pictures, eight pictures, or sixteen pictures corresponding tovideo signals outputted from video cameras can be displayed according toa combination of quad images.

For example, when a multiplexed image consisting of sixteen picturescorresponding to video signals captured by video cameras is displayedbased on the quad image combination, four quad units QUAD1-QUAD4 areconfigured as shown in FIG. 1. In this case, frame memories fm1-fm4 areprovided to configure the respective quad images. A frame memory fm5 anda quad unit QUAD5 are provided to combine quad video data from therespective quad units QUAD1-QUAD4 and to process the combined quad videodata so that a multiplexed image consisting of sixteen picturescorresponding to the video data can be displayed.

As the number of quad units is increased, the number of frame memoriesneeds to be increased to configure a multiplexed image consisting ofsixteen pictures. A last stage of the conventional video monitoringsystem includes another quad unit QUAD5 for processing the quad videodata from the respective quad units in addition to the four quad unitsQUAD1-QUAD4, and another frame memory fm5 for configuring themultiplexed image consisting of sixteen pictures in addition to theframe memories fm1-fm4. As a result, there is a problem in that thevideo monitoring system requires a complex configuration to configure amultiplexed image consisting of more than four pictures, resulting inincreased cost for the system configuration.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above problems, andthe present invention provides a video monitoring system using daisychain, which can display a multiplexed image consisting of more thanfour pictures with its simple configuration by bypassing video signalscaptured by a plurality of video cameras through several stages.

The present invention also provides a video monitoring system usingdaisy chain, which can display a multiplexed image having a plurality ofpictures corresponding to a plurality of channels by arbitrarilyextending the number of pictures constituting the multiplexed imageusing a single memory.

According to an aspect of the present invention, there is provided avideo monitoring system configuring and displaying a multiplexed imageconsisting of a plurality of pictures each corresponding to a videosignal captured by each of video cameras, including: A/D(Analog/Digital) converters each of which converts a channel videosignal outputted from the corresponding video camera into digital videodata; one or more slave video signal processors coupled in a daisy chainmanner each of which scales down digital video data of individualchannels outputted through a video source channel from each of the A/Dconverters, outputs the scaled-down digital video data to a first bypasschannel of the slave video signal processor, and re-collects and outputsdigital video data outputted through a first bypass channel of apreceding slave video signal processor and collected digital video dataoutputted through a second bypass channel of the preceding slave videosignal processor to a second bypass channel of the slave video signalprocessor; a master video signal processor that scales down digitalvideo data of individual channels outputted through a video sourcechannel from A/D converters, records on a frame memory the scaled-downdigital video data and digital video data outputted from first andsecond bypass channels of a last slave video signal processor, andconfigures and outputs video data corresponding to a multiplexed image;and a D/A (Digital/Analog) converter converting the video datacorresponding to the multiplexed image into an analog video signal andoutputting the analog video signal to a video display device.

The slave video signal processor scales down the digital video datacorresponding to the video signals that are captured by each of thevideo cameras and inputted through the video source channel, and outputsthe scaled-down digital video data. In addition, the slave video signalprocessor bypasses the digital video data outputted from another slavevideo signal processor placed at its preceding stage, and outputs thebypassed digital video data to another slave video signal processorplaced at its following stage. The master video signal processor recordson the frame memory the digital video data corresponding to the videosignals that are captured by individual video cameras and inputtedthrough its video source channel, and the digital video data bypassedfrom the slave video signal processor placed at its preceding stage,configures and outputs a multiplexed image to a video display device.Therefore, the video monitoring system displays the multiplexed imagewith its simple configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a view showing a conventional video monitoring systemincluding a plurality of quad units;

FIG. 2 is a view showing a video monitoring system using daisy chain inaccordance with a first embodiment of the present invention;

FIG. 3 is a block diagram illustrating a video signal processor forimplementing the video monitoring system shown in FIG. 2;

FIG. 4 is a view explaining a signal transfer procedure when the videosignal processor shown in FIG. 3 is employed as a slave video signalprocessor;

FIG. 5 is a view explaining a signal transfer procedure when the videosignal processor shown in FIG. 3 is employed as a master video signalprocessor;

FIG. 6 is a view showing a video monitoring system using daisy chain inaccordance with a second embodiment of the present invention; and

FIG. 7 is a view showing a video monitoring system using daisy chain inaccordance with a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Now, exemplary embodiments of the present invention will be described indetail with reference to the annexed drawings. In the followingdescription, a detailed description of known functions andconfigurations incorporated herein will be omitted when it may make thesubject matter of the present invention rather unclear.

FIG. 2 is a view showing a video monitoring system using daisy chain inaccordance with a first embodiment of the present invention. In moredetail, FIG. 2 is a view showing a video monitoring system fordisplaying a multiplexed image consisting of sixteen pictures on a videodisplay device.

As shown in FIG. 2, the video monitoring system for displaying amultiplexed image consisting of sixteen pictures includes three slavevideo signal processors 18, 20 and 22 and one master video signalprocessor 24. The slave video signal processors 18, 20 and 22 and mastervideo signal processor 24 may include the same components as describedbelow.

Referring to FIG. 2, A/D (Analog/Digital) converters 10, 12, 14 and 16are coupled to video source channels of the slave video signalprocessors 18, 20 and 22 and master video signal processor 24. The A/Dconverters 10, 12, 14 and 16 convert channel video signals outputtedfrom video cameras vc1-vc16 into digital video data.

The slave video signal processors 18, 20 and 22 scale down the digitalvideo data of individual channels outputted from the A/D converters 10,12 and 14 through the video source channels and then output thescaled-down digital video data to a first bypass channel V1, V3 and V5.The slave video signal processors 18, 20 and 22 collect the digitalvideo data of the video source channels outputted through the firstbypass channel N.C., V1 and V3 and the digital video data outputtedthrough a second bypass channel N.C., V2 and V4 and then output thecollected digital video data to the second bypass channel V2, V4 and V6,respectively. The slave video signal processors 18, 20 and 22 arecoupled to one another by the daisy chain.

The master video signal processor 24 scales down the digital video dataoutputted from the A/D converters 16 through a video source channel. Themaster video signal processor 24 records the digital video dataoutputted from the first bypass channel V5 and the second bypass channelV6 coupled to the third slave video signal processor 22, placed at apreceding stage of the master video signal processor 24, in a framememory 26. The frame memory 26 stores the digital video data forconfiguring a multiplexed image consisting of a plurality of pictures.For reference, a memory controller equipped with the master video signalprocessor 24 controls access to the frame memory 26.

A D/A (Digital/Analog) converter 28 converts the video datacorresponding to the multiplexed image outputted from the master videosignal processor 24 into an analog video signal. For reference, “N.C.”of FIG. 1 is an abbreviation of “No Connection”. Configurations of theslave video signal processors 18, 20 and 22 and master video signalprocessor 24 in the video monitoring system will be described below indetail.

FIG. 3 is a block diagram illustrating a master or slave video signalprocessor for implementing the video monitoring system shown in FIG. 2.In accordance with an embodiment of the present invention, the slavevideo signal processors 18, 20 and 22 and master video signal processor24 comprise video input controllers 30, horizontal/vertical scalers 32,input buffers 34, a memory controller 36, an output buffer 38, a videooutput controller 40 and a bypass buffer 42, respectively, as shown inFIG. 3.

The video input controllers 30 convert digital video data outputted fromthe A/D converters 10 through the video source channel into a formatsuitable for internal processing. The video input controllers 30 areincluded in a conventional quad chip and operate in the same manner asthose included in the conventional quad chip.

In the video signal processors, the number of video input controllers 30is the same as the number of A/D converters 10.

The horizontal/vertical scalers 32 scale down the digital video dataoutputted from the video input controllers 30 in a horizontal directionor/and in a vertical direction so that the digital video data can bestored as a multiplexed image. It is clear that the horizontal/verticalscalers 32 scale down the digital video data by performing interpolationbetween adjacent digital video data on the basis of scale-down ratios.The scale-down ratios in the horizontal and vertical directions can bevaried according to the number of pictures constituting a multiplexedimage to be displayed on a video display device. In the embodiment ofthe present invention, it is assumed that each slave video signalprocessor configures a multiplexed image consisting of four pictures. Inthe video signal processors, the number of horizontal/vertical scalers32 is the same as the number of video cameras.

The input buffer 34 temporarily stores the video data outputted from thehorizontal/vertical scalers 32 and then outputs the video data throughtwo channels. One of the two channels is a first bypass channel (BypassVideo Out) and the other channel is needed in the memory controller 36reading the video data.

The memory controller 36 reads the video data from the input buffer 34in burst mode and records the video data at frame memory addressesdesignated channel by channel. The recorded video data is read out sothat it can be displayed in real time. In accordance with the presentinvention, the slave video signal processors 18, 20 and 22 are notdirectly connected to the memory controller 36 and only the master videosignal processor 24 is directly connected to the memory controller 36.

The output buffer 38 temporarily stores the video data corresponding toa multiplexed image to be displayed on a display device. The videooutput controller 40 combines supplementary information (including timeinformation, channel information, etc.) with the video data of themultiplexed image outputted from the output buffer 38 and outputs thevideo data combined with the supplementary information. The video dataoutputted from the video output controller 40 is converted into ananalog video signal by the D/A converter 28 and then the analog videosignal is outputted to the video display device.

The bypass buffer 42 receives and temporarily stores the video data froma first bypass channel (Bypass Video In) and a second bypass channel(Bypass Video In) coupled to a slave video signal processor placed atits preceding stage. Then, the bypass buffer 42 outputs the stored videodata to the memory controller 36 and through the second bypass channel(Bypass Video Out). That is, the bypass buffer 42 collects the videodata inputted through the bypass channels by temporarily storing andsequentially outputting the video data.

As described above, the slave video signal processors 18, 20 and 22 andthe master video signal processor 24 according to the embodiment of thepresent invention may be composed of the same components as one another.However, when the video signal processor is employed as the slave videosignal processor, it uses only the video data outputted through thefirst bypass channel coupled to an output terminal of the input buffer34.

FIG. 4 is a view explaining a signal transfer procedure when the videosignal processor shown in FIG. 3 is employed as a slave video signalprocessor. FIG. 5 is a view explaining a signal transfer procedure whenthe video signal processor shown in FIG. 3 is employed as a master videosignal processor.

In other words, when the video signal processor shown in FIG. 3 isemployed as the slave video signal processor, the digital video datainputted through the video source channels is transferred to anotherslave video signal processor or the master video signal processor placedat the following stage of the slave video signal processor through avideo input controller 30, a horizontal/vertical scaler 32, an inputbuffer 34 and a first bypass channel (Bypass Video Out). Then, the slavevideo signal processor collects the digital video data inputted throughthe first bypass channel and a second bypass channel coupled to anotherslave video signal processor placed at its preceding stage and thenoutputs it through the second bypass channel. That is, since the slavevideo signal processor collects the video data inputted through thevideo source channel placed at its preceding stage, it can be configuredas shown in FIG. 4 or FIG. 3.

The video signal processor shown in FIG. 5 represents a case in whichthe video signal processor shown in FIG. 3 is operated as the mastervideo signal processor. Video signals outputted from video camerasvc13-vc16 are inputted into a video source channel through A/Dconverters 10. Then, the digital video data inputted through the videosource channels is stored in a frame memory 26 through video inputcontrollers 30, horizontal/vertical scalers 32 and input buffers 34. Thedigital video data outputted through bypass channels V5 and V6, coupledto another slave video signal processor placed at the preceding stage ofthe video signal processor shown in FIG. 5, is stored in the framememory 26 through a bypass buffer 42 by a frame controller 36.Accordingly, the video data stored in the frame memory 26 is controlledby the memory controller 36 and outputted through an output buffer 38and a video output controller 40 to the outside.

The operation of the video monitoring system shown in FIG. 2 will bedescribed in which the slave video signal processors 18, 20 and 22 andthe master video signal processor 24 are coupled by the daisy chain.

First, video signals captured by four video cameras vc1-vc4 areconverted into digital video data by A/D converters 10. Then, thedigital video data is inputted into a video source channel coupled tothe slave video signal processor 18. Then, the slave video signalprocessor 18 scales down the size of the video data to be suitable for amultiplexed image consisting of sixteen pictures and outputs thescaled-down video data. The scaled-down video data is outputted to afirst bypass channel V1 through input buffers 34 and then transferred tothe slave video signal processor 20. Since no video signal processor isconnected to the preceding stage of the slave video signal processor 18,there is no data to be transferred to the slave video signal processor20 through a second bypass channel V2.

On the other hand, video signals captured by four video cameras vc5-vc8are converted into digital video data by A/D converters 12. Then, thedigital video data is inputted into a video source channel coupled tothe slave video signal processor 20. Then, the slave video signalprocessor 20 scales down the size of the video data to be suitable for amultiplexed image consisting of sixteen pictures and outputs thescaled-down video data. The scaled-down video data is output to thefirst bypass channel V3 (vc5-vc8) through input buffers 34 and thentransferred to the slave video signal processor 22.

After processing the video signals captured by the video camerasvc1-vc4, the slave video signal processor 20 receives the digital videodata through the first bypass channel V1 coupled to the slave videosignal processor 18 placed at its preceding stage. The digital videodata is transferred to the second bypass channel V4 (vc1-vc4) throughthe bypass buffer 42.

After processing video signals captured by the video cameras vc5-vc8,the slave video signal processor 22 receives the scaled-down video datathrough the first bypass channel V3. Further, after processing videosignals captured by the video cameras vc1-vc4, the slave video signalprocessor 22 receives the scaled-down video data through the secondbypass channel V4. The video data outputted from two bypass channels V3and V4 is collected in the bypass buffer 42 and then transferred to themaster video signal processor 24 through the second bypass channel V6(vc1-vc8). The digital video data inputted into the video source channelcoupled to the slave video signal processor 22 is transferred to themaster video signal processor 24 through the first bypass channel V5(vc9-vc12) according to the above-mentioned operation.

Accordingly, the bypass buffer 42 in the master video signal processor24 collects the digital video data (vc1-vc12) inputted through the firstbypass channel V5 and the second bypass channel V6 and then outputs itto the memory controller 36. The digital video data of the video sourcechannel corresponding to the video signals captured by the video camerasvc13-vc16 is scaled down and then transferred to the memory controller36. The memory controller 36 in the master video signal processor 24records the digital video data of sixteen channels at designatedaddresses of the frame memory 26 to configure the multiplexed imageconsisting of sixteen pictures. The video data corresponding to themultiplexed image consisting of sixteen pictures stored in the framememory 26 is accessed by the memory controller 36 and then transferredto an external D/A converter 28 through the video output controller 40,such that the multiplexed image consisting of sixteen pictures isdisplayed on the video display device.

Since the frame memory needs not to be included in each of the videosignal processors to configure the multiplexed image consisting ofsixteen pictures and an additional video signal processor is not neededto configure the multiplexed image consisting of sixteen pictures at alast stage of the video monitoring system, it is possible to provide avideo monitoring system having a simple configuration.

Further, since a video signal processor having the same components isused either as a slave video signal processor or a master video signalprocessor, it is possible to simplify the system configuration and tosimply extend or scale down the system.

Although the video monitoring system configuring and displaying amultiplexed image consisting of sixteen pictures has been describedabove, it can display a multiplexed image consisting of twelve picturesby combining two slave video signal processors 18 and 20 and one mastervideo signal processor 24 through the daisy chain as shown in FIG. 6.Further, the video monitoring system can display a multiplexed imageconsisting of eight pictures by combining one slave video signalprocessor 18 and one master video signal processor 24 through daisychain as shown in FIG. 7.

According to the present invention, the frame memory needs not to beincluded in each of video signal processors to configure a multiplexedimage consisting of sixteen pictures, and an additional video signalprocessor is not needed to configure the multiplexed image consisting ofsixteen pictures at a last stage of the video monitoring system.Accordingly, it is possible to provide the video monitoring systemhaving a simple configuration.

Further, since video signal processors having the same components areused either as a slave video signal processor or a master video signalprocessor, it is possible to simplify the system configuration and tosimply extend or scale down the system.

While the present invention has been described with reference toexemplary embodiments thereof, it will be understood by those skilled inthe art that various changes in form and details may be made thereinwithout departing from the scope of the present invention as defined bythe following claims.

1. A video monitoring system for configuring and displaying amultiplexed image consisting of a plurality of pictures eachcorresponding to a video signal captured by each of video cameras,comprising: A/D (Analog/Digital) converters, each of which converts achannel video signal outputted from the corresponding video camera intodigital video data and outputs the digital video data through a videosource channel; one or more slave video signal processors coupled in adaisy chain manner, each of which scales down digital video data ofindividual channels outputted through the video source channels fromeach of the A/D converters, outputs the scaled-down digital video datato a first bypass channel of the slave video signal processor,re-collects digital video data outputted through a first bypass channelof a preceding slave video signal processor and collected digital videodata outputted through a second bypass channel of the preceding slavevideo signal processor, and outputs the re-collected data to a secondbypass channel of the slave video signal processor; a master videosignal processor that scales down the digital video data of individualchannels outputted through a video source channel from the A/Dconverters, records on a frame memory the scaled-down digital video dataand digital video data outputted from first and second bypass channelsof a previous slave video signal processor, and configures and outputsvideo data corresponding to a multiplexed image; and a D/A(Digital/Analog) converter for converting the video data correspondingto the multiplexed image into an analog video signal and outputting theanalog video signal to a video display device.
 2. The video monitoringsystem of claim 1, wherein each slave video signal processor includes:video input controllers converting digital video data outputted throughthe video source channel from the A/D converter to a format suitable forinternal processing; horizontal/vertical scalers for scaling down thedigital video data outputted from the video input controllers inhorizontal and vertical directions; input buffers temporarily storingscaled down digital video data outputted from the horizontal/verticalscalers and outputting the scaled-down digital video data to the firstbypass channel; and a bypass buffer temporarily storing the digitalvideo data outputted from the first and second bypass channels of thepreceding slave video signal processor and outputting the stored digitalvideo data to the second bypass channel of the present slave videosignal processor.
 3. The video monitoring system of claim 2, wherein themaster video signal processor includes: video input controllersconverting digital video data outputted through the video source channelfrom the A/D converter to a format suitable for internal processing;horizontal/vertical scalers scaling down the digital video dataoutputted from each of the video input controllers in horizontal andvertical directions; an input buffer temporarily storing the scaled-downdigital video data outputted from the horizontal/vertical scalers andoutputting the scaled-down digital video data through one or morechannels; a bypass buffer temporarily storing the digital video dataoutputted from the first and second bypass channels of a preceding slavevideo signal processor and outputting the digital video data to one ormore channels; a memory controller for reading the video data from theinput buffer and the bypass buffer in burst mode, recording the videodata at designated addresses of the frame memory to configure video datacorresponding to a multiplexed image, and reading and outputting theconfigured video data so that the multiplexed image can be displayed inreal time; an output buffer temporarily storing video data correspondingto the multiplexed image outputted from the memory controller; and avideo output controller combining the video data outputted from theoutput buffer with supplementary information and outputting the videodata combined with the supplementary information.
 4. The videomonitoring system of claim 2, wherein the master video signal processorincludes: video input controllers for extending the digital video dataof the video source channel outputted from each A/D converter andseparating and controlling synchronous signals; horizontal/verticalscalers for reducing the digital video data outputted from each videoinput controller in horizontal and vertical directions; input buffersfor temporarily storing the reduced digital video data outputted fromeach of the horizontal/vertical scalers and outputting the storeddigital video data through one or more channels; a bypass buffer fortemporarily storing the digital video data outputted from the firstbypass channel and the second bypass channel placed at the front stageof the master video signal processor and outputting the stored digitalvideo data through one or more channels; a memory controller for readingthe video data from each input buffer and the bypass buffer on aburst-unit basis, recording the read video data at designation addressesof the frame memory, configuring multiple channel divided displayscreens and reading out the recorded video data so that the configuredmultiple divided display screens can be displayed in real time; anoutput buffer for storing the video data of one display screen outputtedfrom the memory controller; and a video output controller for combiningsupplementary information with the video data of the one display screenoutputted from the output buffer and outputting the video data and thesupplementary information.
 5. The video monitoring system of claim 2,wherein the number of the slave video signal processors is one, two orthree, and the one, two or three slave video signal processors arecoupled to the master video signal processor by the daisy chain.
 6. Thevideo monitoring system of claim 1, wherein the master video signalprocessor includes: video input controllers converting digital videodata outputted through the video source channel from the A/D converterto a format suitable for internal processing; horizontal/verticalscalers scaling down the digital video data outputted from each of thevideo input controllers in horizontal and vertical directions; an inputbuffer temporarily storing the scaled-down digital video data outputtedfrom the horizontal/vertical scalers and outputting the scaled-downdigital video data through one or more channels; a bypass buffertemporarily storing digital video data outputted from first and secondbypass channels of a preceding slave video signal processor andoutputting the digital video data to one or more channels; a memorycontroller for reading the video data from the input buffer and thebypass buffer in burst mode, recording the video data at designatedaddresses of the frame memory to configure video data corresponding to amultiplexed image, and reading and outputting the configured video dataso that the multiplexed image can be displayed in real time; an outputbuffer temporarily storing video data corresponding to the multiplexedimage outputted from the memory controller; and a video outputcontroller combining the video data outputted from the output bufferwith supplementary information and outputting the video data combinedwith the supplementary information.
 7. A video monitoring systemconfiguring and displaying a multiplexed image consisting of a pluralityof pictures each corresponding to a video signal captured by each ofvideo cameras, comprising: A/D converters, each of which converts achannel video signal outputted from the corresponding video camera intodigital video data and outputs the digital data through a video sourcechannel; one or more slave video signal processors coupled in a daisychain manner, each of which scales down digital video data of individualchannels outputted through a video source channel from each of the A/Dconverters, outputs the scaled-down digital video data to a first bypasschannel of the slave video signal processor, re-collects digital videodata outputted through a first bypass channel of a preceding slave videosignal processor and collected digital video data outputted through asecond bypass channel of the preceding slave video signal processor, andoutputs the re-collected data to a second bypass channel of the slavevideo signal processor; a master video signal processor that scales downdigital video data of individual channels outputted through a videosource channel from the A/D converters, configures video datacorresponding to a multiplexed image from the scaled-down digital videodata and digital video data outputted from first and second bypasschannels of a last slave video signal processor, and outputs the videodata corresponding to the multiplexed image; and a D/A converterconverting the video data corresponding to the multiplexed image into ananalog video signal and outputting the analog video signal to a videodisplay device.
 8. A video monitoring system configuring and displayinga multiplexed image consisting of a plurality of pictures eachcorresponding to a video signal captured by each of video cameras,comprising: Digital A/D converters, each of which converts a channelvideo signal outputted from the corresponding video camera into digitalvideo data and outputs the digital video data through a video sourcechannel; one or more slave video signal processors coupled in a daisychain manner, each of which scales down digital video data of individualchannels output through a video source channel from each of the A/Dconverters according to a scale-down ratio based on the number ofpictures constituting the multiplexed image, outputs the scaled-downdigital video data to a first bypass channel of the slave video signalprocessor, re-collects digital video data outputted through a firstbypass channel of a preceding slave video signal processor and collecteddigital video data outputted through a second bypass channel of thepreceding slave video signal processor, and outputs the re-collecteddata to a second bypass channel of the slave video signal processor; amaster video signal processor that scales down digital video data ofindividual channels outputted through a video source channel from theA/D converters according to a scale-down ratio based on the number ofpictures constituting a multiplexed image, configures video datacorresponding to a multiplexed image from the scaled-down digital videodata and digital video data outputted from first and second bypasschannels of a previous slave video signal processor, and outputs thevideo data corresponding to the multiplexed image; and a D/A converterconverting the video data corresponding to the multiplexed image into ananalog video signal and outputting the analog video signal to a videodisplay device.